-------------------------------------------------------------------------------
--
-- Title       : test
-- Design      : HDLeditor_demo
-- Author      : aldec
-- Company     : Microsoft
--
-------------------------------------------------------------------------------
--
-- File        : c:\Users\vincenti\Desktop\testworkspace\wkspace\src\test.vhd
-- Generated   : Tue Feb 10 16:24:39 2015
-- From        : interface description file
-- By          : Itf2Vhdl ver. 1.22
--
-------------------------------------------------------------------------------
--
-- Description : 
--
-------------------------------------------------------------------------------

--{{ Section below this comment is automatically maintained
--   and may be overwritten
--{entity {test} architecture {test}}

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity test is
	port(
		alpha : in std_logic;
		beta : in std_logic;
		zeta : out std_logic;
		clk: in std_logic;  
		reset: in std_logic;
		din: in std_logic;  
		dout: out std_logic	 
		
		);
end test;

--}} End of automatically maintained section

architecture test of test is
begin
	
	xnor_gate: process( alpha, beta )
		
	begin  
		zeta <= alpha xnor beta;
	end process;
	
	
	process (clk, reset)
	begin
		if reset='1' then	--asynchronous reset active high
			dout <= '0';
		elsif (clk'event and clk='1') then  --clk rising edge
			dout <= din;
		end if;
	end process;
	
end test;
